1. Field of the Invention
The present invention relates to an image display device which facilitates production of high-quality images, and particularly to an image display device capable of reducing power consumption by fabricating memories for displaying images with TFTs (Thin Film Transistors).
2. Description of Prior Art
In a first conventional technique, an active matrix type display device using TFTs incorporates therein a nonvolatile memory composed of TFTs fabricated on the same substrate and in the same fabrication processes as for pixel-driving TFTs, as disclosed in Japanese Patent Laid-Open Publication Nos. 2,000-252,373 and 2,001-326,289, for example. FIG. 16 illustrates a configuration of the display device employing the first conventional technique. In a display section 100, pixels 104 are arranged in a matrix fashion (in order to simplify the diagram, only one of the pixels 104 is shown). In both the above publications, used as the nonvolatile semiconductor memory is an EEPROM (Electrically Erasable Programmable Read Only Memory) having charge-storage layers and floating gates, and disposed around the display section 100 are a signal-related circuit 101, a scanning-related circuit 102, and a nonvolatile semiconductor memory 103. This configuration makes it possible to incorporate the function of the nonvolatile semiconductor memory without use of LSI (Large-Scale Integration) into the display device.
In a second conventional technique, a display device uses as a frame memory a semiconductor memory composed of TFTs fabricated on the same substrate and in the same fabrication processes as for pixel-driving TFTs, as disclosed in detail in Japanese Patent Laid-Open Publication No. Hei 11-85,065, for example. FIG. 17 illustrates a configuration of this display device. Pixels 115 are arranged in a matrix fashion in a display region 110, are coupled to a D/A (Digital-to-Analog) converter circuit 113 via signal lines 116, and are also coupled to a scanning-related circuit 114 via gate lines 117. Coupled to the D/A converter circuit 113 are a frame memory 112 and a signal-related circuit 111. The frame memory 112 is a DRAM (Dynamic Random Access Memory) having memory cells each of which is comprised of one transistor and a capacitor, stores display information corresponding to one frame, and thereby is capable of continuing displaying even when externally writing of display information is discontinued.
In a third conventional technique, a display device uses as one-bit pixel memories semiconductor memories composed of TFTs fabricated on the same substrate and in the same fabrication processes as for pixel-driving TFTS, as disclosed in detail in Japanese Patent Laid-Open Publication No. Hei 8-286,170, for example. FIG. 18 illustrates a configuration of this display device. Pixels 123 are arranged in a matrix fashion in a display region 120, are coupled to a scanning-related circuit 122 via gate lines 126 and ac-driving signal lines 127, and are also coupled to a signal-related circuit 121 via positive-polarity signal lines 124 and negative-polarity signal lines 125. Each of the pixels 123 is provided with a one-bit SRAM (Static Random Access Memory). With this configuration, this liquid crystal display panel is capable of continuing a one-bit image display even when outputting of data to the display section 120 is discontinued.
The memory circuits in the above-described conventional techniques are formed by using Si semiconductor TFTS. In the above conventional techniques, various kinds of memory functions can be incorporated into display devices by using Si semiconductor TFTS, thereby making possible the highly functional display devices and reduction in power consumption.